The 2nm inflection
Gate-all-around FETs are moving from research to volume manufacturing, and complementary FETs are the leading candidate for the node after. Both transitions are triggering a fresh wave of process, integration, and metrology filings from the foundries and their equipment suppliers.
Filing patterns
TSMC, Samsung, and Intel dominate the process claims. ASML, Applied Materials, Lam, and Tokyo Electron are filing heavily around EUV patterning, atomic-layer etch, and selective deposition — the enabling steps that make GAAFET and CFET manufacturable. The interesting activity is in the EDA layer, where Synopsys and Cadence are building patent moats around design-for-CFET tooling.
Implications for licensing
Expect a licensing cycle around 2028-2030 as CFET enters production and the standards-adjacent claims (bonding, back-side power delivery, hybrid integration) mature. Portfolio owners should prepare evidence packages now.
