A
Structure, process and circuit overlap
A single semiconductor invention may be claimed as a device structure, a fabrication method, a circuit or a system. Relevant earlier disclosures can sit in any of these framings, so the search follows each.
HBM · Chiplets · Packaging · TSV · Memory
Investigate earlier disclosures before you tape out, file or commit.
Semiconductor innovation now spans devices, processes, packaging, memory and interfaces. Hashi IP Solutions runs technology-focused prior art searches across patent and relevant non-patent literature, so semiconductor R&D and IP teams can review earlier disclosures with structured, traceable findings.
Industry challenge
A
A single semiconductor invention may be claimed as a device structure, a fabrication method, a circuit or a system. Relevant earlier disclosures can sit in any of these framings, so the search follows each.
B
Interposers, bridges, redistribution layers, hybrid bonding and micro-bumps are described in many ways across companies, eras and regions. Searches expand terms, acronyms and classifications deliberately.
C
Much semiconductor knowledge is published in conference papers, journals and standards-related documents, not only in patents. These can matter as much as patent publications.
D
Packaging, thermal, signal-integrity, memory-controller and interface ideas often interact. Comparable solutions may be filed under a neighbouring layer of the stack.
E
A structured search helps teams find relevant disclosures and inform patentability and product decisions. It does not guarantee patentability, freedom to operate, grant or the avoidance of infringement.
Coverage
01
Stacked DRAM architectures, base and logic dies, memory-stack thermal management, refresh and repair schemes, wide-I/O interfaces and controller–PHY integration.
02
Die partitioning, die-to-die interconnects, chiplet interface concepts, known-good-die testing, disaggregated SoC architectures and multi-die system design.
03
2.5D and 3D packaging, silicon and organic interposers, embedded bridges, fan-out wafer-level packaging, redistribution layers, hybrid bonding, warpage control and package-level thermal solutions.
Advanced packaging insight04
TSV formation, liners and barriers, fill materials, keep-out zones, stress mitigation, wafer thinning, reveal processes and TSV-based stacking.
05
DRAM, NAND and NOR flash, 3D NAND, emerging non-volatile memories, memory cells, sensing and programming schemes, error correction and memory-controller techniques.
06
High-speed serial and parallel interfaces, memory interfaces, SerDes, equalisation, clocking, signal and power integrity, and on-package and off-package interconnects.
07
Transistor architectures such as FinFET and gate-all-around, lithography-related methods, deposition, etching, metallisation, back-side power delivery and process integration.
08
Power devices including wide-bandgap materials, power management ICs, data converters, RF front-end circuits and mixed-signal design.
09
Processing-near-memory, compute-in-memory, accelerator microarchitectures, on-chip networks and memory-hierarchy innovations.
Software prior art search010
Design-for-test, built-in self-test, wafer and package test, failure analysis, reliability mechanisms and yield-improvement methods.
Sources & terminology
JEDEC & IEEE
Standards-related documents from bodies such as JEDEC and IEEE can describe interface, memory and test concepts with dates attached. They can help identify earlier technical disclosures where they are publicly accessible and in scope.
Some standards documents are restricted, paywalled or revised over time. Publication and availability dates are recorded where they can be established, and gaps are noted rather than assumed.
A prior art search does not determine whether a patent is essential to a standard, nor does it provide licensing or legal conclusions. Those questions require separate analysis and qualified professional review.
Search objectives
Investigate earlier disclosures relevant to the technical features of a proposed semiconductor invention before or during drafting.
Patentability searchExplore existing approaches to a defined device, process, packaging or interface problem.
Help engineering teams understand relevant earlier solutions before committing to a new architecture or process direction.
Look for earlier disclosures relevant to the claims of an identified patent, within an agreed scope.
Invalidity searchWhen the question is where a technology area is moving rather than what came before one invention, a landscape study fits better.
Patent landscapeWorkflow
01
Identify the device, process or system level, the technical problem, the proposed solution, key features and the search objective.
02
Establish concepts, synonyms, classifications, jurisdictions, date constraints and relevant non-patent sources.
03
Investigate relevant patent publications and available family information with a strategy tailored to the invention.
04
Review appropriate conference, journal, standards-related and product literature where relevant and accessible.
05
Organise the most relevant results, explain technical similarities and differences, and provide traceable references for review.
Deliverables
Who it's for
Investigate earlier disclosures before advancing device, circuit or architecture innovations into filings.
Review prior disclosures on DRAM, HBM, NAND, emerging memories and controller techniques.
Explore earlier packaging, interposer, bonding and thermal disclosures.
Investigate process, materials and integration approaches.
Assess chiplet, accelerator and memory-hierarchy concepts against earlier work.
Review disclosures relevant to tools, materials and process steps you supply.
Obtain structured technical findings to inform further professional review.
Why Hashi IP
Scope starts from the actual device, process or system problem and the invention's features.
Searches consider device, process, packaging, circuit and system framings of the same idea.
Patent publications and appropriate non-patent sources are considered within the agreed scope.
Findings are organised so engineering and IP stakeholders can review them quickly.
Findings can lead into patentability, invalidity, landscape or analytics work where useful.
Start a search
Please don't share confidential invention details when booking. A short, non-confidential summary is enough to scope the work. See our privacy policy.
FAQ
A structured investigation of patent and relevant non-patent literature for earlier disclosures related to the technical features of a semiconductor invention, such as a device structure, process, package or interface.
Yes. Searches can cover stacked DRAM, base dies, TSV-based stacking, thermal management, repair schemes and memory interfaces, using expanded terminology and classifications.
Yes — including die-to-die interconnects, interposers, embedded bridges, fan-out packaging, redistribution layers and hybrid bonding, framed as structures, processes or systems as appropriate.
The invention is broken into formation, fill, stress, thinning and stacking aspects, each searched with technical synonyms and classifications across patent and technical literature.
They can, where documents are publicly accessible and in scope. Some standards documents are restricted or revised over time, so availability and dates are recorded where they can be established.
No. Essentiality and licensing questions require separate analysis and qualified professional review. A prior art search identifies earlier disclosures only.
Many semiconductor concepts first appear in conference papers, journals and technical documents. Excluding them can leave relevant earlier disclosures unexamined.
Yes. Because the same idea may be claimed as a structure, a method or a circuit, the search considers each framing relevant to the invention.
No. A prior art search looks at earlier disclosures. A freedom-to-operate search examines in-force claims a product might fall within, and any infringement opinion remains with qualified patent counsel.
No search can promise exhaustive discovery. Results depend on the agreed scope, source accessibility, publication dates and terminology used in earlier documents.
A short, non-confidential outline is enough to start: the technology area, the problem addressed, the general approach, target jurisdictions and the decision the search should support. Detailed disclosures follow once confidentiality terms are in place.
Typically before drafting an application, before committing to a new architecture or process direction, or when assessing an identified patent. Timing and scope depend on the invention and the objective.